This invention relates to a current mirror replica system and more particularly to such a system which combines the function of a current mirror and that of a replica biasing circuit in one system.
It is sometimes necessary to provide a circuit or system with a bias current. Replica biasing is a technique for providing such current by creating a desired reference current flow in a reference current circuit, and then creating a replica of that reference current to make the required bias current, and supplying that replica bias current to the load circuit. When the desired bias current is large, it may be desirable to have the replicated current be a multiple of the reference current. This would be the case, for example, when total current drain on the system is a concern, so that a small reference current in the reference current circuit would economize current use.
The replica current may be created by a current mirror. Current mirror circuits, in their various forms, have certain shortcomings, but still manage to work well in some applications. Conventional current mirror circuits, however, encounter significant drawbacks when the replicated current is a multiple of the reference current. In such circuits, the effects of base currents flowing between the transistors carrying the replica current and the transistors creating the reference current become non-negligible, and significant deviations in the replica current can arise.
What is needed is a current mirror replica biasing system in which the reference current circuit may operate at a fraction of the current of the active circuit, and in which the required bias current is created using a current mirror which dependably provides a multiple of the reference current in the reference current circuit. Another desirable feature of such a current mirror replica biasing system in some applications would be to have its output be proportional to absolute temperature, or other desired function.
It is therefore an object of this invention to provide a simpler, more accurate combined current mirror replica biasing system.
It is a further object of this invention to provide such a current mirror replica biasing system which is capable of high ratio current mirroring.
It is a further object of this invention to provide such a current mirror replica biasing system that combines the functions of both a current mirror and replica biasing circuit in a single, more efficient design.
It is a further object of this invention to provide a current mirror replica biasing system which has the ability to drive a load with an output that is substantially proportional to absolute temperature.
The invention results from the realization that a truly simpler and more accurate replica biasing system which is accurate even at large current ratios can be effected by de-coupling the reference current side of the circuit from the effects of the output side of the circuit; in particular, by incorporating the current reference transistor into the current mirror circuit so that the base current of the current reference transistor becomes the exclusive input mirrored by the current mirror and delivered to the base of the output transistor to produce an operating current in the output transistor which is in the same proportion to the operating current in the current reference transistor as the desired current ratio, be it unity or greater or lesser than unity. The only exception to this exclusivity is the addition of currents proportional to the base current.
This invention features a reference current circuit in which is established a reference current, which current has a known and fixed ratio to the desired bias current output. The sample base current of a transistor in the reference current circuit is connected exclusively to the input of a current mirror circuit, which replicates the base current in the reference current circuit. An output buffer circuit buffers the output of the current mirror and transmits the replicated current to an output transistor to control the operation of the output transistor. This circuit can also deliver a replicated current to an additional circuit for further processing prior to delivering that current to the output transistor or other load. Each transistor has a first and second current terminal and a control terminal.
In a preferred embodiment, the reference current circuit may be as simple as a transistor of opposite polarity to the current mirror transistors, and a resistor. The reference current circuit may further include one or more other transistors and resistors to increase the quantity of the reference current, or to render the output of this invention proportional to absolute temperature, or some other desired function. The current mirror circuit may include two transistors with interconnected control terminals, and one transistor may be a scaled-up version of the other. The output buffer circuit may consist of a transistor of like polarity to the current mirror transistors and opposite polarity to the reference current transistor, and of like size to the output transistor of the two current mirror transistors. The current reference transistor and output transistor are ratio matched; that is the output transistor is of like polarity and functional characteristics of the reference current transistor, but of like size to the output buffer transistor.
This invention also features a current mirror replica biasing system including a current mirror circuit having a controlling transistor and a controlled transistor with their emitters connected to like polarity voltages and operating at a predetermined current ratio. There is an output buffering transistor of like polarity to the controlling and controlled transistors. The output buffering transistor has one of its load terminals connected to the controlled transistor and the bases of the controlling transistor and controlled transistor. There is also a current reference transistor and an output transistor both of opposite polarity to the controlling, controlled and output buffering transistors. The current reference transistor has its collector connected to a voltage of like polarity to the voltage connected to the emitters of the controlling and controlled transistors and its base connected to the collector of the controlling transistor. The base of the output transistor is connected to the collector of the output buffering transistor and the collector of the output transistor is connected to the circuit to be biased. There is a current source for generating a desired current having the first terminal and the second terminal with the second of the terminals connected to a common voltage closer to ground than the voltage is connected to the emitters of the controlling and controlled transistors and the collector of the current reference transistor. The first of the terminals is interconnected to the emitter of the current reference transistor and the base of the output buffering transistor. In a preferred embodiment, the controlled and controlling transistors may have equal current densities in the areas of their emitters and may be in a predetermined current ratio. The controlled and controlling transistors may have their emitters connected to voltages of like polarity but of different magnitude, the difference in voltage defining the ratio of the predetermined current ratios. The transistors may be bipolar transistors. The controlled, controlling and output buffering transistors may be PNPs and the current reference and output transistors may be NPNs. The transistors may be bipolar transistors with the controlled, controlling and output buffering transistors being NPNs and the current reference and output transistors being PNPs. The current source may be a resistor. The current source may include a first resistor having a first terminal and a second terminal. There may be a sixth transistor of like polarity to the current reference transistor, a second resistor and a third resistor where the collector of the sixth transistor is interconnected to the emitter of the current reference transistor and the base of the output buffering transistor and the emitter of the sixth transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor may be connected to the common voltage and the second resistor and third resistor may be connected as a voltage divider between the common voltage and the voltage of like polarity to that of the controlling and controlled transistors. The base of the sixth transistor may be interconnected with the center of the voltage divider.
The invention also features a current mirror replica biasing system including a current mirror circuit having a controlling transistor and a controlled transistor with their emitters connected to like polarity voltages and operating in a predetermined current ratio. There is an output buffering transistor of like polarity to the controlling and controlled transistors. The output buffering output transistor has one of its load terminals connected to the collector of the controlled transistor. There is first resistor having a first and second terminal, a second resistor having a first and second terminal, and a third resistor having a first and second terminal. The current reference transistor of opposite polarity to the controlling, controlled and output buffering transistors has its collector connected to a voltage of like polarity to that of the controlling and controlled transistors and its base connected to the collector of the controlling transistor. There is an output transistor of like polarity to the current reference transistor. The emitter of output transistor is connected to a voltage less than the voltages connected to the controlling, controlled and current reference transistors and the collector of the output transistor is connected to the circuit to be biased. There is a sixth transistor of like polarity to the current reference transistor. The collector of the sixth transistor is interconnected to the emitter of the current reference transistor and the base of the output buffering transistor. The emitter of the sixth transistor is connected to the first terminal of the first resistor and the second terminal of the first resistor is connected to a voltage less than the voltages connected to the controlling, controlled and current reference transistors. There is a seventh transistor of like polarity to the current reference transistor. The emitter of the seventh transistor is connected to the base of the sixth transistor. The collector of the seventh transistor is interconnected to the base of the current reference transistor and the collector of the controlling transistor. The second and third resistors are connected as a voltage divider between a voltage of like polarity to that of the controlling and controlled transistors and a voltage less than such voltages. The base of the seventh transistor is interconnected with an intermediate terminal of the voltage divider.
The invention also features a method of creating a bias current including establishing in a reference transistor a reference current of known magnitude; using a current mirror to mirror exclusively the base current of the reference transistor; and feeding the mirrored current into the base of an output transistor.